NVIDIA、アジェンティックAI向けCPU「Vera」発表

Agentic AI shifts more of the critical execution path onto the CPU. Agents operate in sandboxes to execute code, invoke tools, retrieve context, interact with databases, and analyze results before returning information to the model. As these loops run concurrently across an AI factory, CPU performance increasingly shapes both per-agent responsiveness and overall factory throughput.

This creates a different CPU design point. Agent workloads depend on:

• Strong single-thread performance, even when the socket is fully loaded.

• Sufficient memory bandwidth per core to keep many active execution contexts supplied with data.

• Predictable latency under concurrency, so agent steps complete consistently.

• Efficient handling of irregular control flow, long dependency chains, and pointer-heavy data structures.

These requirements differ from traditional cloud CPU designs, which often prioritize core density and throughput across more uniform workloads. Agentic AI instead places greater value on sustained per-thread progress across the sequential, branch-heavy, and latency-sensitive software paths within each agent loop.

NVIDIA Vera CPU was built for this class of workload, with the Olympus core at the center of its design. This post examines the Olympus core architecture, multithreading approach, coherency fabric, memory subsystem, and secure scale-up connectivity that enable high single-thread performance at AI-factory scale. For a deeper technical discussion, see the accompanying NVIDIA Vera CPU white paper.

Designing a core for maximum single-threaded agentic performance

Olympus was developed through extreme co-design across the Vera Rubin platform, spanning CPUs, GPUs, networking, storage, memory systems, and software. This system-level approach enabled NVIDIA to optimize the AI factory as a whole, not just the CPU in isolation. As agentic AI and reinforcement learning place more pressure on CPU-side execution, Olympus was built to accelerate the irregular, branch-heavy, and latency-sensitive software paths that increasingly shape end-to-end performance.

The Olympus core is the compute engine of the NVIDIA Vera CPU, designed from the ground up to maximize instructions per cycle (IPC) for highly concurrent AI infrastructure workloads. It combines high single-thread performance, wide instruction throughput, deep out-of-order execution, and advanced memory acceleration technologies to efficiently execute agentic AI, reinforcement learning, data analytics, and large-scale software workloads.

Olympus consists of the following blocks, as shown in Figure 1.

• Front end: Optimized branch predictors

• Mid core: Critical path acceleration

• Execution engine: Complex vector optimization

• Cache subsystem: Latency optimized instruction and data paths

Front end

The Olympus front end is built to keep the core supplied with useful instructions across large, branch-heavy software stacks. Workloads such as agent runtimes, interpreters, compilers, graph analytics, and data-processing frameworks often combine large instruction footprints with frequent control-flow changes, which can leave execution resources underutilized. Olympus addresses these challenges with advanced branch prediction, high-bandwidth instruction fetch, and a 10-wide decode engine that delivers more instructions to the core each cycle.

At the center of this approach is the Olympus branch prediction subsystem, which includes a neural branch predictor designed to improve accuracy on difficult, statistically biased branch patterns. By reducing wrong-path execution and supporting up to two taken branches per cycle, it helps sustain control-flow throughput when software behavior is irregular. Combined with the wide decode path, these capabilities enable Olympus to maintain stronger front-end throughput for latency-sensitive workloads, including agentic AI and reinforcement-learning applications where efficient handling of complex control flow matters most.

Mid core

Agentic workloads often follow long chains of dependent work: interpreting code, traversing objects, managing runtime state, processing tool outputs, and navigating graph-like data structures. In these paths, performance depends not only on instruction fetch, but on the core’s ability to uncover independent work while earlier instructions wait on branches, memory, or dependency resolution.

The Olympus mid core is designed to expose and accelerate this hidden parallelism. A wide rename and allocation engine maps decoded instructions to physical resources, while a large reorder buffer and extensive physical-register capacity keep more instructions in flight for deeper out-of-order execution. Dependency-breaking capabilities—including memory renaming, value prediction, and critical-path acceleration—help reduce stalls from pointer-heavy code, serialized memory operations, and long dependency chains.

Together, these features keep the execution engine productive, improve IPC, and strengthen single-thread performance across the irregular software paths common in agents, RL environments, and modern AI infrastructure.

Execution engine

Agentic workloads require more than a wide front end. Once instructions enter the core, the CPU must efficiently execute a changing mix of integer operations, branches, vector work, and memory accesses without creating new bottlenecks. Traditional x86 server CPUs often rely on higher clock frequencies to improve single-thread responsiveness, but agentic workloads are frequently constrained by irregular control flow, long dependency chains, and memory latency. These challenges demand higher IPC, not frequency alone.

The Olympus Execution Engine turns a wide instruction supply into productive execution. It dynamically schedules operations across a broad set of integer, branch, vector, floating-point, cryptographic, load, and store resources, supported by a wide backend and deep out-of-order execution. This balanced design helps Olympus efficiently handle branch-heavy software, vectorized data processing, AI preprocessing, encryption, compression, analytics, and other memory-intensive workloads.

Cache subsystem

Agents frequently operate on data structures that don’t fit cleanly in the cache, including runtime objects, retrieval indexes, tool state, graph structures, sparse data, databases, and environment memory. Traditional cache and prefetch designs work well for regular streaming access patterns, but they’re less effective when each address depends on the result of a previous memory lookup, as is common in pointer-heavy and graph-like agent workflows.

The Olympus cache subsystem is designed to reduce these stalls and keep the execution engine supplied with instructions and data. It combines a deep cache hierarchy, memory disambiguation, and multiple hardware prefetch engines. Olympus also includes a graph prefetcher designed to improve performance on data-intensive graph and analytics workloads.

Together, these capabilities reduce effective memory latency and increase memory-level parallelism, helping agents, graph analytics, and data-processing workloads spend less time waiting on irregular memory accesses and more time doing useful work.

Multithreading innovations designed for tool calling and reinforcement learning

Multithreading is important for agent workloads, which are often bursty, event-driven, and interleaved with background system activity. A typical sandbox may run a primary execution path while handling asynchronous I/O, timers, runtime services, networking, logging, memory management, and tool orchestration. A second hardware thread enables the CPU to absorb this supporting work locally, improving utilization and responsiveness while reducing how often the primary agent thread must yield, migrate, or wait.

Traditional simultaneous multithreading, or SMT, improves utilization by enabling two hardware threads to share a core, but this sharing can introduce contention. In densely threaded sandbox environments, threads can compete for branch prediction, decode bandwidth, execution resources, load/store capacity, cache, and memory bandwidth. This creates a noisy-neighbor effect within the core, where activity on one thread can reduce the performance of the other. For agentic AI, RL environments, and cloud services, this variability matters because tail latency can directly affect throughput and quality of service.

The Vera CPU takes a different approach with NVIDIA Spatial Multithreading (SMT). Rather than relying solely on opportunistic resource sharing, the wide Olympus core is designed to partition resources more effectively across two hardware threads. This enables Olympus to operate as a high-throughput single-threaded core when maximum per-thread performance is needed, with the sibling thread handling management activity, or as two more isolated execution contexts when higher thread density is required.

The result is strong per-thread performance, improved utilization, and more predictable behavior under load. With 88 Olympus cores and 176 SMT threads, the Vera CPU can support large numbers of concurrent agent tasks while reducing thread-to-thread interference and delivering more consistent latency and throughput.

Sustaining agentic AI performance with coherent fabric and high-bandwidth memory

A high-IPC core delivers its full value only when the rest of the processor can keep it supplied. Agentic AI, reinforcement learning, graph analytics, and data-processing workloads often rely on large working sets and irregular access patterns, making fabric bandwidth, cache access, memory bandwidth, and latency as important as execution width.

Vera CPU pairs the Olympus core with the NVIDIA Scalable Coherency Fabric (SCF) and SOCAMM2 (Small Outline Compression Attached Memory Module) LPDDR5X memory to create a more balanced platform for high-throughput CPU execution at AI-factory scale.

NVIDIA Scalable Coherency Fabric

The NVIDIA Scalable Coherency Fabric is the Vera CPU communication backbone, connecting Olympus cores, shared cache, memory controllers, I/O, and NVLink-C2C interfaces through a coherent, high-bandwidth on-die fabric. It provides up to 3.4 TB/s of fabric bandwidth and integrates a 164 MB unified L3 cache across all cores. By placing cache and fabric resources on a monolithic compute die, Vera CPU avoids the die-hop latency and variability common in fragmented chiplet designs, supporting more predictable access to shared data across the processor.

This is particularly valuable for agent workloads, which frequently exchange state, traverse shared data structures, and move among runtime, retrieval, analytics, and orchestration code. The SCF helps reduce contention, improve cache sharing, and maintain coherent access across CPU resources, while serving as the integration point for NVLink-C2C connectivity to GPUs and scale-up platforms.

SOCAMM2 LPDDR5X memory

Vera CPU uses SOCAMM2 LPDDR5X memory to provide the bandwidth, efficiency, and capacity required for AI infrastructure. The memory subsystem delivers up to 1.2 TB/s of aggregate bandwidth, or up to 14 GB/s per core, helping each Olympus core sustain useful work under high concurrency. Compared with traditional DDR5 and MRDIMM-based server designs, SOCAMM2 LPDDR5X delivers this bandwidth at substantially lower memory power, reducing platform power while keeping cores supplied across bandwidth-intensive AI, analytics, graph, and RL workloads.

SOCAMM2 also brings enterprise serviceability to LPDDR memory. Rather than using soldered-down LPDDR, Vera CPU uses modular, field-replaceable memory modules that retain the short electrical paths needed for high-speed LPDDR5X while supporting datacenter deployment models. The result is a memory architecture that combines high bandwidth, strong power efficiency, and extensive Reliability, Availability, and Serviceability (RAS) capabilities, which are essential for scaling CPU performance across AI factories.

Moving agentic AI data faster, more securely, and at scale

A high-performance CPU must do more than execute instructions quickly. It must also move data securely and efficiently across the AI factory. Modern AI systems rely on the CPU to coordinate accelerators, memory, storage, networking, and other processors, making scale-up connectivity and I/O bandwidth central to overall system performance.

Vera CPU brings together coherent NVIDIA NVLink-C2C, dual-socket scaling, PCIe 6.4, CXL 3.1, and Confidential Computing in a balanced platform architecture. These capabilities support secure, high-bandwidth data movement across next-generation AI infrastructure.

Dual-socket scaling

Vera CPU scales from single-socket deployments to a coherent dual-socket platform using second-generation NVLink-C2C for high-bandwidth socket-to-socket connectivity. This enables both CPUs to operate as a unified system, with coherent data sharing and predictable scale-up performance, while preserving a simpler software model for large CPU workloads across AI factories, HPC, and enterprise computing.

Traditional x86 server CPUs often use chiplet-based designs that can expose multiple NUMA domains within each socket. In large dual-socket systems, this can create a fragmented memory topology, requiring software to carefully place threads, memory, and I/O traffic to avoid remote accesses, additional die hops, and uneven latency.

Vera CPU takes a software-first approach. Each socket presents as a single NUMA domain, creating a clean two-NUMA-node topology in a dual-socket system. Built around a monolithic compute die, unified system-level cache, and coherent fabric, it reduces topology-driven variability and avoids the overhead associated with crossing multiple dies. The result is a dual-socket platform that is easier to program and tune, with more predictable scaling for agentic AI, RL, analytics, and enterprise workloads.

IO connectivity

It includes PCIe 6.4 for high-bandwidth, flexible connectivity to next-generation networking, storage, accelerators, and peripheral devices. A dual-socket configuration provides 176 PCIe lanes, supporting a broad range of platform designs. Vera CPU also supports CXL 3.1, enabling coherent memory expansion, memory pooling, and composable infrastructure for workloads that benefit from larger memory footprints.

Confidential Compute

Vera Rubin NVL72 extends Confidential Computing across scale-up AI infrastructure, protecting data in use across CPUs, coherent GPUs, and interconnects without requiring unnecessary data copies or bounce buffers. Built on Arm CCA/RME with per-VM encryption keys, Vera CPU provides confidential VM isolation, supports secure assignment of TDISP-capable coherent devices, and uses authenticated C2C encryption to protect data across coherent links. Together, these capabilities establish a unified trust domain for secure AI workloads from the server to rack scale.

Delivering leading agentic workload performance

With the Olympus core and fabric, SOCAMM2 LPDDR5X memory, and dual-socket scale-up architecture in place, the next question is how these design choices translate to agentic workload performance. Agentic systems spend significant CPU time in Python execution, code compilation, static analysis, and tool-driven software workflows. These software paths place pressure on large instruction footprints, branch-heavy control flow, dynamic runtime behavior, and long dependency chains.

A key measure is single-thread performance under full socket load. Agentic AI and reinforcement learning commonly run many sandboxes, tools, and environments concurrently. Each agent step depends on strong per-thread progress, but that progress must hold as the full CPU shares socket-level power, cache, memory bandwidth, and fabric resources. Loaded single-thread performance therefore provides a more representative measure of agent throughput, responsiveness, and CPU-side efficiency at AI-factory scale.

To learn more about the NVIDIA Vera CPU architecture and performance, refer to the NVIDIA Vera CPU whitepaper.

SPEC CPU® 2026 results measured internally in July 2026. Refer to the NVIDIA Vera CPU whitepaper for details on performance measurements and configuration.

SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation (www.spec.org).